1. Field of the Invention
This invention relates to packages for integrated-circuits and, more particularly, to an integrated-circuit package which contains two similar integrated-circuit chips positioned back-to-back to increase the capacity of the package.
2. Prior Art
A typical integrated-circuit chip has bonding-pads located around its edges. To connect each bonding-pad to an exterior package pin, a lead frame has bonding fingers, the ends of which are located adjacent to the bonding-pads of the chip and which are connected to external package leads or pins. To connect the bonding-pads on the integrated-circuit chip to the bonding fingers of the lead frame, short, thin bonding wires are connected, or wire-bonded, between each bonding-pad and an adjacent bonding finger. It should be understood that, when the same chips with identical wire-bonding-pads are placed back-to-back in a package, the bonding-pads of one of the chips are reversed with respect to the bonding fingers on the lead frame. However, for an integrated-circuit package with back-to-back chips, it is a requirement that certain external package pins and their corresponding bonding fingers be shared in common. This is difficult to obtain because, in order to connect the reversed bonding-pads to the common bonding fingers of a lead frame, certain bonding wires would have to extend across the chip to reach corresponding reversed bonding-pads on the opposite side of the chip. These thin bonding wires would be very long and consequently subject to a number of problems, including, for example, shorting and wire wash as the chips are encapsulated with a viscous encapsulation material.
To increase the capacity of an integrated-circuit package, two integrated-circuit chips, or chips, can be placed back-to-back. For example, the storage capacity of a memory type of integrated-circuit package can be doubled by using two of the same memory chips in a common package. Certain address pins, output pins, and power pins are common to both chips and can be tied together.
The same integrated-circuit chip cannot be used in a back-to-back package configuration. In a back-to-back configuration, the chips are reversed with respect to each other and same chip pads cannot be connected the same bonding fingers and package pins. As a consequence, if two back-to-back chips are to be used in a package, one of the chips must have a reversed bonding-pads layout. This requires that two different mask sets be used to fabricate two different integrated-circuit chips with different bonding-pad layouts. As the line widths for integrated-circuit processes get smaller and smaller, the corresponding mask sets are significantly increasing in cost, so that having two different mask sets for a back-to-back package of similar integrated-circuits is an expensive undertaking.
What is needed is a cost-effective technique for providing integrated-circuit packages with back-to-back chips which can share common package pins.
It is therefore an object of the invention to provide a cost-effective technique for providing an integrated-circuit chip assembly which has back-to-back chips which are adapted to share common package pins and which are fabricated with the same masks.
In accordance with this and other objects of the invention, a double-sized chip assembly for two back-to-back integrated-circuit chips is provided with a single integrated-circuit layout and a single mask sets. This is accomplished by providing an electrically selectable bonding-pad connection option which provides for a first bonding-pad layout and a second bonding-pad option. One option provides a standard bonding-pad layout and the other option provides a reversed bonding-pad layout.
A double-sized, back-to-back, wire-bonded integrated-circuit chip assembly and method includes a pair of integrated-circuit chips, each having one or more reversible wire-bonding-pads. The chips are adapted to be centrally mounted back-to-back within a lead frame having inwardly-extending bonding fingers. One of the chips has its wire-bonding-pads electrically reversed such that the pads for similar functions are located near each other for wire-bonding to a common bonding finger of a lead frame.
A bonding-option wire-bonding-pad has an external voltage applied to it to indicate whether the integrated-circuit chip is to provide a standard pattern for the reversible wire-bonding-pads, or a reversed option RO pattern for the reversible wire-bonding-pads. A voltage sensor circuit senses the voltage applied to the bonding-option wire-bonding-pad and alternatively generates either a standard NRO gate control signal or a non-standard, reversed RO gate control signal from the voltage state of the bonding-option wire-bonding-pad.
Two or more bonding-option wire-bonding-pads and voltage sensor circuits generate various bonding option logic signals. A logic circuit generates standard NRO and non-standard, reversed RO gate control signals from the one or more bonding option logic signals.
The gate circuits include a complementary-transistor output amplifier.
A double-sized, back-to-back, wire-bonded integrated-circuit chip assembly uses identical chips which are fabricated with the same mask sets. When mounted back-to-back, one of the pair of identical chips has some of its wire-bonding pads reversed to provide connections to commonly used bonding fingers of a lead frame.
An integrated-circuit chip is provided with one or more pairs of reversible wire-bonding-pads to alternatively provide either a standard pattern for the reversible wire-bonding-pads or a non-standard, reversed wire-bonding pattern for the reversible wire-bonding-pads. The chip includes a first wire-bonding-pad and a second wire-bonding-pad. First and second common signal lines are provided on the integrated-circuit chip. Two gate circuits are provided for each wire-bonding-pad. An output signal terminal of each gate circuit is connected to either a first or a second common signal line. A standard wire-bonding configuration control NRO signal operates one of the gate circuits on each wire-bonding pad to provide a standard pattern for the first wire-bonding-pads,. The standard pattern connects one of the wire-bonding-pad to a first common signal line and the second wire-bonding pad to a second wire-bonding pad.
A non-standard, reversed wire-bonding configuration control RO signal operates the other gate circuits on each wire-bonding pad gate circuit to alternatively provide a non-standard, reversed pattern for the wire-bonding-pads.
The NRO signal provides a predetermined standard bonding-pad configuration for the integrated-circuit chip and the RO signal provides a predetermined alternative reversed bonding-pad configuration for the integrated-circuit chip.
A plurality of pairs of first and second wire-bonding-pads can be switched to respective pairs of common signal lines.
A bonding-option wire-bonding-pad is used to program the connections to the bonding-wire pads prior to encapsulation of the chips. A voltage sensor circuit senses the voltage applied to the bonding-option wire-bonding-pad and alternatively generates either a standard NRO gate control signal or a non-standard, reversed RO gate control signal from the voltage state of the bonding-option wire-bonding-pad.
Two or more bonding-option wire-bonding-pads are used for a number of control options, two of which are the NRO and the RO options. Corresponding voltage sensor circuits are provided for respectively sensing the voltage applied to the respective bonding-option wire-bonding-pads. A bonding option logic signal array generates one or more bonding option logic signals and a logic circuit generates standard NRO and non-standard, reversed RO gate control signals from the one or more bonding option logic signals.
One specific embodiment of the invention includes three bonding-option wire-bonding-pads each of which are adapted to having an external voltage applied thereto such that the logic circuit for generating standard NRO and non-standard, reversed RO gate control signals generates the standard NRO and non-standard, reversed RO gate control signals.
The gate circuits include a logic circuit which has a first signal input terminal connected to one of the wire-bonding-pads, which has a second control signal input terminal for receiving a wire-bonding configuration control signal to operate the gate circuit, and which has an output terminal coupled to one of the common signal lines. The gate circuits include a chip enable input terminal for receiving a chip enable signal CE to activate the gate circuits.
In one embodiment of the invention, the logic circuit, a first logic gate has an input terminal connected to a first signal input terminal, a second input terminal connected to the second control signal input terminal, and an output terminal connected to an input terminal of the output driver circuit. The logic circuit also includes a second logic gate, having an input terminal connected through an inverter to the first signal input terminal, having a second input terminal connected through an inverter to the second control signal input terminal, and having an output terminal connected to an input terminal of the output driver circuit. The first logic gate includes a NAND gate and the second logic gate includes a NOR gate. The first logic gate has an input terminal for receiving a chip enable signal CE and the second logic gate has an input terminal for receiving an inverted chip enable signal.
The logic circuit includes an output driver circuit having an input terminal and having an output terminal connected to one of the common signal lines. The output driver circuit includes a complementary-transistor output amplifier which includes a p-channel transistor having a gate terminal connected to an output terminal of the NAND gate and a N-channel transistor connected to an output terminal of the NOR gate.
When the integrated-chips are mounted back-to-back, it is necessary that the wire-bonding-pads for external control signals such as chip-select, write enable, clock, etc., be reversed in accordance with the present invention. Other signals such as memory address and data I/O wire-bonding pads do not absolutely need their wire-bonding pads to be reversed if the pairs of bonding-pads are the same type, that is, address pads or Data input/output I/O pads. Even though one of the chips may have its addresses scrambled, each scrambled address still accesses a uniquely defined memory cell for storing and retrieving I/O signal bits. The memory is unscrambled when the data in the memory cells is addressed and read out using the scrambled address bits. Therefore, reversal of the pads in a pair of pads is not required for control signals as long as the pairs of non-reversed bonding-pads are the same type, that is, in the same family of signals, such as address signals or data I/O signals.